1. Technical Field
The present invention relates to a thin film transistor that is used in liquid crystal displays of the active matrix system, and a method for manufacturing such a thin film transistor.
2. Prior Art
In a liquid crystal display of the active matrix system that uses thin film transistors, liquid crystals are sealed between a TFT array substrate and a counter substrate overlapping the TFT array substrate with a certain distance. On the TFT array substrate, gate electrodes (Y electrodes) and data electrodes (X electrodes) are arranged as a matrix, and thin film transistors (TFTs) are disposed on the intersections of the gate electrodes and the-data electrodes. The thin film transistors control the voltage impressed to the liquid crystals, and the electrooptic effect of the liquid crystals is utilized to enable displaying.
FIGS. 7A and 7B are diagrams illustrating the structure of a top-gate type thin film transistor. Conventionally known structures of thin film transistors are a top-gate (positive-stagger) type structure and a bottom-gate (inverse-stagger) type structure. The structure of a top-gate type thin film transistor will be described referring to FIG. 7A. The top-gate type thin film transistor comprises a light-shield film 102 provided on an insulating substrate 101 such as a glass substrate, on which an insulating film 103 comprising silicon oxide, SiOx, or silicon nitride, SiNx, is formed. Above the insulating film 103, a drain electrode 104 and a source electrode 105 composed of ITO (indium tin oxide) films are disposed of a predetermined channel distance. An amorphous silicon film (a-Si film) 106, as a semiconductor film, that covers both electrodes is provided; a gate insulating film 107 comprising SiOx or SiNx, is provided above the a-Si film 106; and a gate electrode 108 is provided above the gate insulator film 107, to form an island-shaped region called an a-Si island.
As a process for the manufacture of such a thin film transistor, a process known as 7-PEP (PEP: photo engraving process) structure is generally present. In this 7-PEP structure, after a drain electrode 104 and a source electrode 105 composed of ITO film have been patterned, an a-Si film 106 is formed by CVD (chemical vapour deposition), and is patterned in an island shape. A gate insulating film 107 is then formed by CVD, and is patterned to a desired shape. After that, a gate electrode 108, for example of aluminum (Al), is formed by sputtering, and is patterned to complete a TFT.
However, since such a 7-PEP structure required a large number of process steps, a next-generation 4-PEP structure that requires less process steps had been proposed. In the 4-PEP structure, the gate insulating film 107 and the a-Si film 106 underlying the gate electrode 108 are simultaneously etched. That is, the gate electrode 108, the gate insulating film 107, and the a-Si film 106 are sequentially etched in one patterning step using the plated pattern of the gate electrode 108 as a mask. The 4-PEP structure excels in that the manufacturing process is shortened. FIG. 7A shows the top-gate type thin film transistor produced by the shortened manufacturing process.
Here, if the gate electrode 108, the gate insulating film 1.07, and the a-Si film 106 are sequentially eteched in one patterning step, the distance between the end of the gate electrode 108 and the source and drain electrodes 105 and 104 is much shortened as shown in FIG. 7A. That is, this distance is at largest 0.4 xcexcm, easily causing short-circuiting between the end surface of the gate electrode 108 and the source and drain electrodes 105 and 104 due to surface leakage.
To cope with this problem, the gate electrode 108 is over-etched as shown in FIG. 7B. That is, by over-etching the gate electrode 108 during patterning, a length of about 1.5 xcexcm is secured as shown in FIG. 7B, and by clearing a distance of 1.9 xcexcm (about 2 xcexcm) between the source electrode 105 and the drain electrode 104, short-circuiting due to surface leakage is prevented.
The present applicant had presented Japanese Patent Application No. 11-214603 as a technique related to this shortened manufacturing process. The present application provides techniques for decreasing the number of process steps required in the manufacturing process of thin film transistors, as well as for preventing the generation of an abnormal potential due to leakage current from other data lines.
Although, it is not related to decrease in the number of process steps at all, the background art, related to the present invention includes Japanese Patent No. 2522364, and Published Unexamined Patent Application Nos. 1-149480 and 4-367276.
As described above, the over-etching of the gate line at the time of forming the gate electrode 108 of a top-gate type TFT, and the island cutting using a resist mask (not shown) for forming the gate electrode 108 (etching of the gate insulating film 107 and the a-Si film 106) enable the simplificaiton of the process and the prevention of short-circuiting due to surface leakage.
However, it has now been found that the above-described method might result in the occurrence of leakage in the island portion not covered with the gate electrode 108 (floating island).
FIGS. 8A and 8B are diagrams that illustrate the states where the floating island portion has been formed. The circumference region of the gate electrode 108 shown in FIGS. 8A and 8b is the floating island portion 109. Although electrodes are normally disposed above and beneath an a-Si film, the gate electrode 108 is not formed above or beneath the a-Si film 106 that constitutes this floating island portion 109, which unique as the usage of a-Si. Therefore, voltage is not controlled in this floating island portion 109. That is, the floating island portion 109 is not covered with the gate electrode 108, and is in the state where portions nearer the end are more difficult to be controlled by the gate voltage of the gate electrode 108. The detection of leakage paths using OBIC (optically beam induced current) analysis revealed that leakage occurred due to the voltage between the source electrode 105 and the drain electrode 104 at the portion in the floating island 109 between the source electrode 105 and the drain electrode 104, above which or beneath which the gate electrode 108 is not formed, that is, the hatched area shown in FIGS. 8A and 8B. When leakage occurs at the leakage portion 110, i.e. the hatched area, voltage cannot be controlled between the source electrode 105 and the drain electrode 104, and the problem such as the discoloration of pixels due to an abnormal voltage has arisen.
Therefore, the present invention is achieved to solve the above technical problems and the object of the present invention is to reduce leakage current in a floating island portion formed in a thin film transistor.
A thin film transistor to which the present invention is applied comprises a source electrode and a drain electrode disposed above an insulating substrate at a predetermined interval; a semiconductor film disposed in relation to the source and drain electrodes; a gate insulating film overlapping the semiconductor film; and a gate electrode overlapping the gate insulator film. The semiconductor film has a portion which is disposed between the source electrode and the drain electrode, and above which or beneath which the gate electrode is not formed. A P-type impurity is implanted into the portion.
This P-type impurity is characterized in being boron ion. Boron ion is one of lightest ions as P-type impurities, and is preferable in that it can be implanted into a semiconductor film with a high power. Especially when boron ion is implanted into the semiconductor film from the top of a gate insulating film the light boron ion is preferable because it must be implanted into the semiconductor film through this gate insulating film.
Also, this semiconductor film is characterized in that it is provided with a floating island portion formed around said gate electrode and patterned larger than the gate electrode by a predetermined dimension. This is preferable in that, for example, short-circuiting due to surface leakage between the patterned end surface of the gate electrode and the source and the drain electrodes can be prevented, when a semiconductor film is formed in the same pattern as the gate electrode pattern by a shortened manufacturing step and the leakage current between the source and drain electrodes generated through this floating island portion can be prevented.
Also, a thin film transistor to which the present invention is applied comprises a source electrode and a drain electrode disposed above an insulating substrate at a predetermined interval; a semiconductor film in relation to the source and drain electrodes; a gate insulating film overlapping the semiconductor film; and a gate electrode overlapping the gate insulator film. The semiconductor film has a portion which is disposed between the source electrode and the drain electrode, and above which or beneath which the gate electrode is not formed, a polymer structural film is formed on a patterned end surface of this semiconductor film.
In other words, the polymer structural film formed on a patterned end surface of this semiconductor film is characterized in being a leakage preventing film in which a polymer structure is bonded to the cut sections of silicon.
From a different viewpoint, a thin film transistor to which the present invention is applied comprises a source electrode and a drain electrode disposed above an insulating substrate at a predetermined interval; a semiconductor film disposed in relation to the source and drain electrodes; a gate insulating film overlapping the semiconductor film; and a gate electrode overlapping the gate insulator film. The semiconductor film is provided with a measure preventing the leakage current between the source electrode and the drain electrode on a portion above which or beneath which the gate electrode is not formed, or the patterned end surface of the semiconductor film.
If the leakage current preventing measure provided to this semiconductor film is characterized in being a measure for elevating the threshold voltage (Vth) in relation to the portion above which or beneath which the gate electrode is not formed, it is preferable in that leakage paths are substantially eliminated in relation to the floating portion above which or beneath which the gate electrode is not formed.
Also, if the leakage current preventing measure provided to this semiconductor film is characterized by a measure for removing the positive charge of the patterned end surface, it is preferable in that the induction of the conductive electron that causes leakage can be prevented.
In these inventions, it is sufficient if the source electrode and the drain electrode are formed xe2x80x9cabovexe2x80x9d the insulating substrate, and these inventions can be applied to either a top-gate type TFT provided with these electrodes on the insulating substrate side, above which a gate electrode is provided; or a bottom-gate type TFT provided with a gate electrode on the insulating substrate side, above which source and drain electrodes are formed. The expression of xe2x80x9coverlappingxe2x80x9d contains not only overlying, but also underlying, and it is not necessary to contact with each other, but the laminated construction with other materials intervening in between may be used.
On the other hand, when the present invention is viewed from the manufacturing method, a method for manufacturing a thin film transistor in the present invention comprises a step of forming a gate electrode, a semiconductor film, a source electrode, and a drain electrode on a substrate; and a step of implanting a P-type impurity into the semiconductor film formed in the above step at least in a portion between the source and drain electrodes above which or beneath which the gate electrode is not formed.
Also, a method for manufacturing a thin film transistor in the present invention comprises a first step of forming a gate electrode, a semiconductor film, a source electrode, and a drain electrode on a substrate; and a second step of forming a polymer structural film on the end surface of the semiconductor film formed in the above step.
This first step is characterized by comprising forming floating island portion of said semiconductor film above which or beneath which said gate electrode is not formed.
Furthermore, a method for manufacturing a thin film transistor in the present invention comprises a light-shield film deposition step of depositing a light-shield film of a predetermined shape on an insulating substrate; and insulating film formation step of forming an insulating film that covers the light-shield film on the insulating substrate; a source and drain electrodes formation step of forming a source electrode and a drain electrode consisting of metal films that have a predetermined line width and length, and disposed above the insulating substrate at a predetermined interval; a semiconductor and insulating films formation step of sequentially forming a semiconductor film and a gate insulating film above the source electrode and the drain electrode; a gate electrode deposition step of depositing a metal film for the gate electrode above the gate insulating film; a gate electrode patterning step of providing a resist mask for masking the gate electrode above the metal film for the gate electrode, and for patterning the gate electrode using the resist mask; a step of patterning the semiconductor film and the gate insulating film using the resist mask; a step of peeling off the resist mask; and a boron ion implanting step of implanting boron ions into the gate insulator film and the semiconductor film. According to this manufacturing method, since the semiconductor film and the like can be patterned using the resist mask used in the patterning of the gate electrode, the number of process steps required in the TFT manufacturing process can be reduced, and the leakage current between the source and drain electrodes can be minimized.
If this gate electrode-patterning step is characterized in a step of patterning the gate electrode by over-etching the metal film for the gate electrode in relation to the resist mask, the number of process steps can be reduced, and also short-circuiting due to surface leakage between the gate electrode and the source and drain electrodes can be prevented.
Also, if the boron ion implanting step is characterized by a step of implanting at least 1xc3x971018 atoms/cm3 of the boron ions into the semiconductor film, leakage current can be decreased to a drivable range.
The method for manufacturing a thin film transistor according to the present invention can be characterized by comprising a terminating treatment step of the terminating treatment for cut sections of silicon for the patterned end surface of the semiconductor film in place of, or in addition to, the above-described boron ion implanting step. By such a constitution, a TFT that excels in holding characteristics can be formed without increasing the auxiliary capacity.
This terminating treatment can be characterized in an HMDS treatment to the formed thin film transistor substrate. Such a treatment can terminate the cut sections of silicon by converting to silanol, and enables the manufacture of a TFT that has a high leakage reducing effect in a simple process.